Target devices such as field programmable gate arrays (FPGAs), structured application specific integrated circuits (ASICs), and ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of a large system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) compilation flow is hardware description language (HDL) compilation. HDL compilation involves performing synthesis, placement, routing, and timing analysis of the system on the target device.
Some target devices include dynamically reconfigurable logic blocks. Dynamically reconfigurable logic blocks are modifiable to perform alternative functionalities while other parts of the system are operating. Dynamically reconfigurable logic blocks typically implement independent sections of the system that need not be active during an entire application runtime. By realizing hardware sharing, a system utilizing dynamically reconfigurable logic blocks may benefit from a reduction in device count, power consumption, and cost. Compared to static reconfigurable logic blocks, dynamically reconfigurable logic blocks offer the added advantage of allowing unaffected portions of a system to continue to operate during reconfiguration without loss of performance or functionality.
When creating and optimizing a design for a system that includes dynamically reconfigurable logic blocks on a target device, many EDA tools take into consideration only an initial configuration of dynamically reconfigurable logic when performing timing analysis.